TED develops Inrevium evaluation board
Tokyo Electron Device Limited (TED) has developed the Inrevium TB-OP-FCRAM evaluation board for FCRAM
Although DDR2 SDRAM is the current mainstream technology in the DRAM market, its use in digital consumer electronic products requires the mounting of multiple chips to obtain adequate data bandwidth.
This causes problems such as an increase in power consumption because of the termination resistor required and the space of footprint associated with the large package size.
The 256Mbit FCRAM released by Fujitsu Microelectronics in June 2008 has 64-bit bus architecture.
This means it can operate at a lower frequency while still providing the same data transfer capacity as SDRAM that uses 16 or 32-bit bus.
This lower frequency eliminates the need for an external termination resistor and reduces the power consumption by up to 1W (approximately 70 per cent), compared to two pieces of 16-bit bus width DDR2 SDRAM of equivalent performance.
The Inrevium TB-OP-FCRAM includes a Virtex-5 FPGA XC5VLX50-1FFG676C and 256Mbit FCRAM and allows users who are developing SoC to perform interface evaluations using FCRAM at an early development stage.
Publication date: 12.09.2008
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